1. Field
The systems and methods described in this patent document relate generally to memory systems and more specifically to the interaction of logic devices with memory systems that include cache memory.
2. Description of the Related Art
Many electrical or computer systems exist that comprise logic devices, such as micro-processors, micro-controllers, and others, that utilize system memory that comprises both a primary memory subsystem and a cache memory subsystem. Cache subsystems are typically used to decrease the access time for a logic device to acquire information stored in memory. It is desirable for the cache to hold data that has a high probability of being wanted next by the processor so less time is spent accessing the other memory, such as the primary memory, which may have a longer access time than the cache memory.
In many systems data retrieved from primary memory is written to cache memory such that this data may be retrieved from cache memory instead of from the primary memory the next time it is required by the logic device. Thus, the cache memory may be checked for data prior to performing a read of the primary memory and data is written to the cache memory after a write to the primary memory.
In some systems all or part of the cache memory is disabled when the primary non-fast read-write memory is being accessed for its status or configuration. Sometimes this disabling is limited to that part of the cache memory that shadows the non-fast read-write memory. In some systems a software process locates and then invalidates any lines in the cache memory that correspond to the part of the non-fast read-write memory that was programmed. Also, in some systems the whole cache memory is invalidated when part of the non-fast read-write memory is being programmed.
The invalidation of lines of cache memory is also performed in some multi-processor systems. In these systems the processors often share a common primary memory. For example, processor A writes to the shared primary memory. This data is then read by processor B and written to the cache memory in processor B. Upon a subsequent write of data to the same location of primary memory by processor A the previous data in the cache memory of processor B must be invalidated. In these cases “snooping” of the memory bus used to communicate with the primary memory is often performed to monitor accesses to the primary memory. The corresponding line of cache memory in the respective cache memory is then invalidated.